IRDS Assignment
Beyond CMOS
Ashwini Singh
chandel
244102402
Scope- As dimensional scaling of CMOS will eventually approach fundamental limits, new Information processing devices and micro architecture for both existing and new function are being explored.
Current State- As the CMOS scaling is going below 10nm the efficiency and performance of the devices are saturating. Currently below 10nm the there is no significant advantage of efficiency and performance.
Challenges – ① Scaling limit of SRAM and flash. in 2D. Identify high speed, high density, low power volatile and non-volatile memories.
② Develop new material to replace silicon to extend CMOS Scaling.
③ continue functional scaling of information processing technologies beyond ultimately scaled CMOS.
④ Incorporating functionalities that do not necessarily scale according to moores law.
⑤. Identify emerging devices that can implement computing function more efficiently than CMOS.
Solutions – Emerging technologies.
① Memory devices – (a) spin transfer torque MRAM (b) Spin orbit torque MRAM. ② Voltage controlled magnetic anisotropy @OxRAM @Bipolar Filamentary OxRAM.
⑲ Bipolar Non-filamentary On RAM ⑨ Unipolar-Filamentary On RAM
① conducting bridge memory © Mesomdecular memory
① Ferroelectric memory Ⓚ Mass storage device Ⓛ MOTT memory.
Analog in-memory – RERAM and CBRAM, Phase change memory BCRAM, Magnetic neural devices, Floating gate, capacitor-gate
Charge based analog anacys for vmm.
② Emerging logic and Information processing devices.
@Carbon nanotube FET ⑥7 2D Material channel FIZT.
Tanned FETS
③ Beyond CMOS devices
Spin FET and Spin MOSFET Transistors ⑯ Negative gate capacitacce FET Ⓝ NEMS Switch Ⓛ MOTT FET Ⓞ Topological Insulator electronic device Ⓟ Spin Wared device Ⓠ Enitonic device.
④ Transistor laser ⓕ Magnto electric logic ⓖ Domain wall logic ☑ Spintorque Majority gate.
Beyond CMOS devices for more than Moore Application
@PUFS – @STTRAM to create domain wall memory puf.
Memresistors
RNGS-CRRAMis proposed.
© Harware security – Tunable polarity (Carbonnarotube, graphos, SINFET, TMP) Polymorphic logic gate, Camouflaging layout.
Prevent side channel attacks – Steep slope Tx., Bell shaped IV, (TFET), SABLOrCBL.
Emerging Material integration.
Challenges – Materials cand processes for performance and power.
Scaling of lateral fin – nanowire FETs, improve copper interconnect, Scaling DRAM/SRAM, for AI and Quantum computing, charge based and non charge base beyoncmeslogic, for monolithically 3D IC.
Solutions-Ge, (-) materials, improved gate.and doping. tech niches forsculing
③ 193nm and Fox entension material for lithography.
③ New interconnect merterid post-Ca. (Sectable)
④ Hetrogenous Integration and packaging materialle (Seetable)
⑤ Fe FET for memory devices, NEM, NOTT, BISFET etc (See table?)
Novel computing paradigms and application pulls
Efficiency and performance
More Moore
trend
Big data
IoT and trillions of edge sensors
Deep learning and artificial intelligence
Exascale supercomputing
Robotics and autonomous systems
Beyond CMOS
Emerging Architectures
Emerging Devices/Processes
Emerging Materials
Size
100 nm
10 nm
1 nm
Relationship of More Moore, Beyond CMOS, and Novel Computing Paradigms and Applications (Courtesy of Japan beyond-CMOS Group)
FE EMIS Emerging materials for memory
Application/Need
Ferroelectric FET
Ferroelectric tunnel junction
Conductive bridge RAM
ReRAM-OxRAM-Filamentary
REAM-OxRAM-Nonfilamentary
Mott memory
Novel magnetic memory
Emerging Material or Process
Solutions
Interface Material: SiO2 or HfAIOx
FE Material: HfO2, HfO2(Si
La doned115ROT209
FEFET BaTiO3, BiFeO3 (tunnel
barrier)
Insulator: GeSe, GeS, AgS, CuS,
AgSe, CuSe, Ta205; Electrode: Ag.
Insulator: HfOx, TaOx, TiOx, NiO.
Flectrode TaN TIN NHA51
Insulator: PrCaMnO3, Nb:SrTiO3, etc;
Electrode: Pt, SrRuO3, etc. [6]
Complex Metal Oxides and Transition
Metal Oxides: e.g. Nd1-x5rxMnO3
and VO2.
Chalcogenides: AM4QS (A-Ga, Ge;
M-V, Nb, Ta. Mo: Q- S. Se)
Voltage torque MRAM: FeCo, CoFeB-
Spin orbit torque MRAM: Pt. B-Ta, B-
Waxveen doned W Inst
Potential Advantages
Excellent endurance
Excellent endurance
Scalability and nonvolatility
Scalability and nonvolatility
Scalability and nonvolatility
Scalability and nonvolatility
Scalability and nonvolatility
Low power and high speed
Challenges/Status
Understanding the origin of FE effect
Lin doned HD21
Depolarization field-control of charge
tranning
Memory retention time and fatigue –
choice of metallic electrode
Maintain FE domain properties in
ultrathin films
Single domain polarization
Scalability, stability and reliability.
Reproducible filament forming
process. Scalability, stability and
Understand the mechanisms for
different materials. Integration of
perovskites with CMOS process [6].
Determining whether the electronic
transition can reversibly occur with or
without the first order structural phase
transition. Determining the thermal
control required for reversible
Need to understand retention and
scaling affects
Need better retention and
demonstration of integration
Need lower resistivity materials to
application/Need
Conductor conducthity improvement
Emerging Material or Process
Barrierless metal conductor (eg.
CuGe, etc.)
Potential Advantages
Cu barrier materials
Lowk ILD
Novel viaz
Novel additives (e.g. CNTs, etc)
2D barrier materials: graphene, h-BN,
TMD
Nanoporous ILD
Mesporous ILD
Novel nolymers
Air gap materials
Carbon nanotubes (CNTs)
Novel interconnects
Carbon nanotubes
Graphene
Challenges Status
Eliminate the need for a barrier layer Integrating novel materials in the
Reduce grain boundary scattering
resistance effects.
Reduce barrier volume of the
interconnect while reducing
interconnect resistance and
capacitance
Reduce intercomect capacitance
High density in small vias
High aspect ratio (AR) via filling
Defect-free metal contacts
Effective Resistivity
Control of chirality
Thermal behavior
conductor, eliminating metal diffusion
and reducing the interconnect
resistance. Continued research is
Effective integration of the novel
materials in the conductor (Cu) and
simultaneously reducing the resistance
of the interconnect. Continued
research is needed. Integration of
CNTs in Cu allowed increased current
density[1] and reduced resistivity[2].
Adhesion to low-k ILD and Cu.
Barrier performance and leakage
current for <2 nm. Barrier
performance in presence of
topography and defects. Continued
research needed
All low k materials have a significant
challenge to maintain dielectric
constant after integration and
processing. Mechanical strength,
adhesion, leakage current,
compatibility with patterning and
packaging processes. Continued
research needed
Air gap pinch off formation control,
stability, barrier integrity,
conformality Contime research
Need of 5-10E12 tubes/cm, tube
diameter <5-3 mm. Ability to grow in-
situ and integrate 1E12 vertically
aligned tubes/cm2 in 70 nm vias with
2.5E12tubes/
repeatable yield [3,4]. 2.5
Need of extremely high aspect ratio
(AR) via hole filling by CNTs.
Selective growth from bottom of the
via hole is required. MWCNTs grown
from the bottom of 90um via hole
Need to produce direct metallic
contacts to all the shells to minimize
risks of resistance, local heating, and
electromigration. Pd to date is the best
Resistances down to 0.05 Ohm in 2.8
um diameter vias (60mm high) filled
All MWCNTs behavior is metallic.
Need to achieve accurate control of
Intrinsic CNT thermal resistance is
low. Thermal interface resistance may
Ability to grow in controlled locations CNTs can be grown in specific
Ability to grow in controlled
directions
Thermal behavior
Effective resistivity
Ability to prepare at controlled
locations
Ability to grow/transfer high-quality
graphene at low temperature
Ability to control thickness
Highly selective etch
Defect-free contacts
Thermal behavior
Effective resistivity
Directional growth of a bundles of
MWNTs is reported. Need higher
growth rate [10]. Top-down approach
to align single-walled carbon
Intrinsic CNT thermal resistance is
low. Thermal interface resistance may
Need to improve the quality of CNTs
Graphene can be grown in specific
locations with patterned catalyst [12].
Transfer of graphene from a different
substrate, followed by its patterning is
also possible [13,14] Graphene
selectively grown on Ni damascene
interconnect patterns on 300mm Si
wafer [15], but quality improvement
Graphene can be grown at 600 C
using Co [16] and Co-Ir alloy [17] as
catalytic layers. With Fe catalyst,
graphene growth at 650 C was
demonstrated [12]. But, the quality
needs improvement. High-quality
multi-layer graphene growth at 1000
C, and subsequent graphene-transfer
Multi-layer graphene with a relatively
uniform thickness can be obtained on
an epitaxial metal catalyst [13], but
Continued research needed to identify
a dielectric etch that doesn’t damage
Continued research needed to produce
good contacts to vertical interconnects
(vias) to minimize risks of resistance
Intrinsic graphene thermal resistance
is low. Thermal interface resistance
The resistivity of multi-layer graphene
grown by CVD is as low as -50
(L). The resistivity can be as
low as 4 µlem by intercalation of
le EMI6 Heterogeneous integration, assembly and packaging materials
Application/Need
Stacked chip adhesives (low power
density)
Stacked chip adhesives (high power
density
Novel printable die attach adhesive
EMI shielding materials
Mold compound
Emerging Material or Process
Solutions
Die attach materials/back side films,
materials for thin packages
Better cooling solutions with low
thickness
Nanoink (with either insulating
particles or conductive particles
depending on the application)
Nanoink
Graphene film (multilayer)
Carbon nanotube composite or CNT
paper
Next generation mold compound
3D electrical interconnects
New polymer with nanofillers
Potential Advantages
Challenges/Status
Using nanoparticles, low BLTs can be
achieved and by increasing their
Low coefficient of thermal expansion loading. CTE can be lowered, but the
(CTE) systems
Low bond line thickness (BLT), low
CTE
Adhesion, electrical properties
(insulating and conductive), thermal
conductivity, particle size smaller than
hand line testes afhand line)
Electrical conductivity
Adhesion
Ion barrier
Electrical insulation and high thermal
conductivity
Need to avoid cracking in bending
stresses with thin silicon, CTE
between silicon and the flexible
substrate and high adhesion to IC
materials. Flow compatible with flip
chip underfill to enable one step (UF
and Mold). Undermold must be void
free!!! Material must be compatible
with stress requirements of thin
High effective thermal conductivity
High interfacial adhesion, high fracture
toughness, low CTE (between Si and
substrate CTE), resistance to
electromigration, low process
temperature, low moisture sensitivity,
stress decoupling canacity
viscosity goes up upon addition of
nanoparticles and their dispersion is
difficult to control at high loadings
Reducing thermal interface resistance
Adhesion, flexibility, strength
Adhesion to polymer package
Defect free graphene. Integration
Integration and cost
Using nanoparticles, low CTEs can be
achieved, but the viscosity goes up
upon addition of nanoparticles and
their dispersion is difficult to control at
high load
ings. In order to achieve high
toughness [to withstand bending
stress), filler-matrix adhesion needs to
be strong (Improved Moisture
Performance)
Achieving high thermal conductivity
High current capacity with reliability
in the use case with low assembly cost.
Thermal & thermal Mechanical Stress
need to be addressed especially for k
<2